This invention relates to a logical comparison device for making a comparison between input logical data and reference logical data for each clock.
In a system for testing logical units, such as, for example, various types of semiconductor integrated circuits, it is necessary to apply a logical pattern to a unit under test and to decide by comparison whether the resulting output logical data derived therefrom is coincident with an expected value or not. In general, the comparison is made for each time slot of data and at each moment of the time slot. The comparison result is usually read in a logical circuit, such as a D flip-flop, and in order for the logical circuit to correctly read therein the input data, it is necessary that the input data lasts for a certain period of time, i.e. for the so-called set-up time T.sub.S. In conventional types of logical comparison devices, input logical data and reference logical data are compared, with their effective lengths both selected equal to one time slot; consequently, near the end of one time slot of the input logical data, that is, in the period of the set-up time T.sub.S preceding the next time slot, the comparison result cannot be read in the logical circuit. Further, when the speed of the input logical data increases to reduce the length T.sub.C, T.sub.C -T.sub.S approaches zero, making it impossible to obtain correct comparison results.